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Samsung Develops Industry’s First 12-Layer 3D-TSV Chip Packaging Technology

Samsung today announced that it has developed the industry’s first 12-layer 3D-TSV (Through Silicon Via) technology. Samsung’s new innovation is considered one of the most challenging packaging technologies for mass production of high-performance chips, as it requires pinpoint accuracy to vertically interconnect 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes, each of which is one-twentieth the thickness of a single strand of human hair.

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The thickness of the package (720㎛) remains the same as current 8-layer High Bandwidth Memory-2 (HBM2) products, which is a substantial advancement in component design. This will help customers release next-generation, high-capacity products with higher performance capacity without having to change their system configuration designs. The Samsung 3D packaging technology also features a shorter data transmission time between chips than the currently existing wire bonding technology, resulting in significantly faster speed and lower power consumption.

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Relying on its 12-layer 3D-TSV technology, Samsung will offer the highest DRAM performance for applications that are data-intensive and extremely high-speed.  By increasing the number of stacked layers from eight to 12, Samsung will soon be able to mass produce 24-gigabyte (GB) High Bandwidth Memory, which provides three times the capacity of 8GB high bandwidth memory on the market today.




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