Toshiba has developed a breakthrough technology that achieves low voltage operation of System LSI, opening the way to reduced power consumption in digital products. The technology secures successful operation of static random access memories (SRAM) at low voltage with an improved circuit design that optimizes voltage control of the bit line and word line. The new technology overcomes the high failure rate that has been the main challenge in achieving practical, low voltage SRAM, and reduces memory cell failure rate by four orders of magnitude at 0.7V. The circuit design can be applied to the memory compiler, software that automatically configures SRAM, contributing to shorter design lead times and bringing an effective solution to the LSI development process.
Toshiba will unveil the new technology on the fourth day of the 2010 International Solid State Circuit Conference (ISSCC), one of the semiconductor industry’s leading international conferences, which is being held in San Francisco, California, U.S.A., from February 7 to February 11.
