Toshiba has developed a breakthrough technology for steep channel impurity distribution that delivers a solution to a key problem for 20nm generation CMOS technology. The technology opens the door to a future generation of LSI fabricated with bulk CMOS technology, the mainstream technology in today’s LSI, by achieving the world’s first practical fabrication process applicable to 20nm generation CMOS devices. The new technology forms three layers on the surface of the channel: epitaxial silicon (Si), carbon-doped silicon (Si:C), and boron-doped Si:C. The top epitaxial Si layer functions as a low resistance path for the electrons and the holes; the intermediate Si:C acts as a defensive layer to prevent impurity diffusion; and the bottom boron-doped Si:C layer suppresses the fixed charge caused by the Si:C layer formation.
Toshiba unveiled the new technology at the 2009 International Electron Devices Meeting (IEDM) held in Baltimore, Maryland, U.S.A. from December 7 to December 9
